The AI semiconductor landscape is evolving beyond the traditional race for the fastest chip. Experts at the GSA Women’s Leadership Initiative event outlined how success now depends on integrating chips within larger systems including packaging, connectivity, and supply chain management.
- AI chips are now engineered as part of broader systems, not standalone devices.
- Optical and advanced packaging technologies are key to overcoming data movement bottlenecks.
- AI-driven design and testing methods reduce manufacturing errors and accelerate development.
What happened
The GSA Women’s Leadership Initiative event brought together semiconductor industry experts who shared insights into how AI is reshaping chip development. Traditionally, semiconductor competition centered on single-chip metrics like raw compute power. Now, the focus has shifted toward the entire system encompassing chiplet packaging, interconnect bandwidth, power management, and supply chain coordination. Qualcomm’s vice president Letizia Giuliano highlighted the trend of optimizing system performance instead of just silicon.
Speakers from Intel, Marvell, Advanced Semiconductor Engineering, GlobalFoundries, and others also explained how product engineering and manufacturing teams must collaborate from the earliest stages. New packaging technologies such as Intel’s EMIB and ASE’s VIPack platforms demonstrate how chiplets are combined into larger, scalable systems. Additionally, AI is being deployed to analyze production data and aid chip design, improving yield and shortening development cycles.
Why it matters
This systemic approach to semiconductor development marks a foundational transformation in how AI hardware is created. Data movement bottlenecks have become a critical limiter of AI performance, dwarfing pure compute improvements. The emergence of optical interconnects combined with copper wiring inside packages and racks is a response to this challenge, enabling higher bandwidth and energy efficiency.
Furthermore, early integration of manufacturing constraints and reliability planning ensures that chips can meet high-volume production demands with fewer defects. AI-assisted testing and design automation promise faster iterations and lower costs. These advances collectively will dictate who leads in AI hardware by delivering scalable, power-efficient, and reliable solutions for complex AI workloads.
What to watch next
Industry observers should monitor how widespread adoption of advanced packaging and optical interconnect technologies evolves, particularly in hyperscale applications. Technologies like Intel’s EMIB and Qualcomm’s High Bandwidth Compute may set new standards for system-level integration that shape future AI infrastructure.
Additionally, the growing role of AI in chip design and testing tools, exemplified by Lattice Semiconductor’s AI design assistant, may revolutionize engineering workflows. Lastly, the development of standards and security for physical AI—autonomous systems interacting with the real world—will be critical as companies collaborate across hardware, software, and firmware domains to build safe, scalable AI solutions.