TSMC is set to revolutionize chip manufacturing with its CoPoS (Chip-on-Panel-on-Substrate) packaging technology, promising significant cost reductions and enhanced performance for advanced AI chips. This approach shifts from traditional wafer processes to rectangular panel fabrication, enabling greater material efficiency and larger package sizes tailored for high-demand AI workloads.
- CoPoS uses rectangular panel-based packaging replacing wafer-level processing
- Targets cost-effective production of ultra-large AI chip packages by 2028
- Enhances performance supporting AI accelerators needing more memory and bandwidth
What happened
TSMC announced progress on its CoPoS technology, a novel chip packaging method that abandons conventional wafer-based manufacturing in favor of panel-level processes. This shift is designed to boost material utilization and enable packaging of significantly larger semiconductor components. The new technique is aimed primarily at meeting the demands of next-generation AI accelerators, which require larger and more complex chip assemblies integrating multiple compute chiplets and high-bandwidth memory.
Industry analysts, including Ming-Chi Kuo, project that CoPoS is on track for mass production around the second half of 2028. Unlike some early speculation, CoPoS does not use glass as a permanent substrate but only temporarily during manufacturing. The final chip packages utilize traditional substrates, ensuring reliability while improving manufacturing economics and reducing waste.
Why it matters
As transistor scaling slows, semiconductor innovation is increasingly focused on packaging and chip integration techniques to sustain performance improvements. CoPoS represents a significant leap in this area by enabling bigger and more cost-effective chip packages, a critical advantage as AI workloads demand expanding memory capacity, compute power, and interconnect bandwidth.
This advanced packaging approach also supports the industry's trend toward modular AI chip designs that incorporate multiple specialized chiplets. By enhancing efficiency in producing these ultra-large packages, CoPoS could accelerate development cycles and reduce costs for AI hardware manufacturers, influencing the competitive dynamics of AI chip markets and suppliers.
What to watch next
The semiconductor sector will be looking closely for further technical disclosures and pilot manufacturing outcomes from TSMC, which will provide clearer insights into CoPoS' scalability, yield, and real-world performance benefits. Adoption by major AI chip developers, such as NVIDIA with its upcoming Feynman processors, will serve as a key validation milestone for this technology.
Moreover, industry observers should monitor how CoPoS fits within TSMC’s broader packaging portfolio, particularly its relationship to existing solutions like CoWoS. The balance and specialization between these technologies will shape the future landscape of AI chip packaging innovation and influence design strategies across the semiconductor ecosystem.